module Testbench;
reg Clock, ENbar;
reg [31:0] addr_bits; 		
wire DQ_RDY;
parameter TRUE   = 1'b1;
parameter FALSE  = 1'b0;
parameter CLOCK_CYCLE  = 20;
parameter CLOCK_WIDTH  = CLOCK_CYCLE/2;
parameter IDLE_CLOCKS  = 2;

reg Access;

L1_data_cache data_cache(addr_bits,ENbar,DQ_RDY);
IOManager ioManager(Access, , );				//Shouldn't we call this inside L1_data_cache?
//
// set up monitor
//
/*
initial
begin
  $display("LRU_bits\t\t\tLRU\t\t\tWay Accessed\t\tNext LRU bits\n");
  $monitor("%b\t\t\t%b\t\t\t%b\t\t\t%b\n", LRU_bits, Way, Curr_way,Next_LRU_bits);
end
*/

//
// Create free running clock
//
initial
begin
  Clock = FALSE;
  ENbar = TRUE;
  addr_bits = FALSE;
  forever #CLOCK_WIDTH Clock = ~Clock;
end


initial
begin

    @(posedge Clock); Access = TRUE;
    @(posedge Clock); Access = FALSE;
    @(posedge Clock); Access = TRUE;
    @(posedge Clock); Access = FALSE;
    @(posedge Clock); Access = TRUE;            
    @(posedge Clock); Access = FALSE;
        
    @(posedge Clock); ENbar = TRUE;       //    ******* TAG ****** | * INDEX *  | OFFSET 
    #(2*CLOCK_CYCLE) {ENbar,addr_bits} = 33'b0_1111_1111_1111_1111_0110_1001_11_001110;
    #(2*CLOCK_CYCLE) ENbar = TRUE;       //    ******* TAG ****** | * INDEX *  | OFFSET 
    #(2*CLOCK_CYCLE) {ENbar,addr_bits} = 33'b0_1111_1111_1111_1111_0110_1000_11_001000;  
    #(2*CLOCK_CYCLE) ENbar = TRUE;  
end

endmodule

